View source for Quickly Setup Tuning Bits For Simulation in Cadence

[[Image:Tuning_bits.png]]<br>
You can make a verilogA model to set up tuning bits. <br>
You dont need to know verilogA. I've made a simple script to do this:  <br>

/afs/eecs.umich.edu/wics/users/odelberg/generate_veriloga_tuning_bits<br>

There are insturctions in the README.

You can use this to generate a symbol. Then press space while highlighting the symbol in schematic to quick generate busses with labels. <br>