Quickly Setup Tuning Bits For Simulation in Cadence

You can make a verilogA model to set up tuning bits.
You dont need to know verilogA. I've made a simple script to do this:

/afs/eecs.umich.edu/wics/users/odelberg/generate_veriloga_tuning_bits

There are insturctions in the README.

You can use this to generate a symbol. Then press space while highlighting the symbol in schematic to quick generate busses with labels.