Digital Flow Tutorial in 65GP
Digital flow for TSMC 65nm GP (cln65gp). Uses HVT std cells.
Make a copy of the flow in your local directory:
/afs/eecs.umich.edu/wics/users/odelberg/DIGITAL_FLOW_N65
Set up the environment:
module load gcc
module load vcs
module load synopsys-synth
module load innovus
module load calibre
To generate SPI:
1. Modify /generators/spi_generator/Make_SPI.py file. Instructions are inside.
2. Run using: python Make_SPI.py
3. Output file is "SPI_slave.sv"
To run verilog simulation:
1. Move all verilog files and testbenches to /sources directory
2. Move to /sim directory
3. Modify the Makefile to point to your top level and testbench.
4. To run type:
make <- simulate, no GUI
make dve <- simulate, with GUI
make clean <- remove run and log files
To run synthesis:
1. Modify /config/design_name.tcl to the name of your top level verilog file.
2. Modify /config/constraints.tcl to the name of your clock signal, clock period, RESETn signal, and any additional clock constraints.
3. Run synthesis in bottom level using command: perl run.pl -d
4. Check all reports to make sure there are no setup timing violations in /reports/synthesis before continuing.
Additional synthesis settings may need be set in /tools/synthesis.tcl
To run APR:
1. Modify /config/apr_init.tcl to specify floorplan variables.
2. Modify /config/pin_map.io for your pin placement. You may use /generators/pin_io_generator/ for big designs.
3. Run apr in bottom level using command: perl run.pl -p
NOTE: there is a suspend point after floorplan in the script to debug. You must manually type resume to continue APR. You can comment out this suspend in /tools/apr.tcl if not wanted.
4. Check all reports sure there are no timing violations or DRC/LVS issues in /reports/apr before continuing.
5. Import design into Cadence same as 427.
For schematic import in Cadence, use: /outputs/apr/DESIGN.apr.lvs.v
For layout import in Cadence, use: /outputs/apr/DESIGN.top_digital.gds
Additional APR settings may need to be set in /tools/apr.tcl
To run DRC/LVS:
1. Use the Makefile in /calibre.
2. Use "make drc" and "make lvs" to run.