VerilogA
In Cadence 6, simulating a VerilogA file is a little more complicated. It turns out that for any cell to simulate, it must have a ".oa" file associated with it. The ".oa" file is typically generated in schematic when you press "Check and Save." If it does not have this ".oa" file, you will receive the following error when you try to run an analog simulation (or actually when you try to netlist).
Missing or corrupt .oa file in cellview...
There are two ways to create this .oa file for your VerilogA file. The first way involves just creating it for an individual VerilogA file. The second way creates ".oa" files for all VerilogA files within a particular library.
Method 1
vmsUpdateCellViews(?lib "mylib" ?cell "buf" ?view "arc_stop")
Method 2
You must load a SKILL script into the CIW window within cadence. This can be done one of two ways. You can enter the following code directly, or you can create a file with extension ".il" that contains this information. Then you can load it into the cadence CIW window using the load command.
procedure(CCScreateOA(lib viewName)
let(()
foreach(cell ddGetObj(lib)~>cells
if(member(viewName cell~>views~>name) then
vmsUpdateCellViews(?lib lib ?cell cell~>name ?view viewName)
)
)
))
If you create a ".il" file you can load it into cadence by typing the following in the CIW window.
load "file_name.il"
Once you have loaded the procedure into cadence you run the following command.
CCScreateOA("mylib" "veriloga")
Notice that you should run these commands before creating a symbol for your VerilogA file. These commands will automatically create a symbol and will ensure that the pins are properly mapped. Also, remember that you will not be able to run a simulation without first doing one of the following. So if your simulation runs, you must have done something right.
References
This information comes from the following cadence support page (reproduced below)
Database and setup requirements for OSS based VHDL netlister
Error Code None Error Message \o ERROR (OSSHNL-381): Missing or corrupt .oa file in cellview
'mylib/buf/arc_stop'. The OSS netlister can only
\o process cellviews that have a valid .oa file. This file can be created by
\o either importing the cellview using tools like 'Verilog In' or 'VHDL IN', or by
\o opening and writing the text file in the Library Manager.
ERROR (VHDL_HNL): VHDL netlister did not find a valid text-view at leaf level for instance 'f6' [VHDL_In.or3:symbol] in cellview [VHDL_In.fulladder:schematic]. Check if you have supplied a correct switch view list and/or you have a text-view(with shadow database) for this cell.
Definition I was using VHDL toolbox to create a vhdl netlist in IC6.1.3 successfully. Now, I have shifted to IC6.1.5. On IC6.1.5 cells which netlisted successfully for me are failing with below messages:
\o ERROR (OSSHNL-381): Missing or corrupt .oa file in cellview
'mylib/buf/arc_stop'. The OSS netlister can only
\o process cellviews that have a valid .oa file. This file can be created by
\o either importing the cellview using tools like 'Verilog In' or 'VHDL IN', or by
\o opening and writing the text file in the Library Manager.
Suddenly my flow has broken. How do I make things work?
Solution In IC6.1.4 and later the VHDL netlister is OSS based, like the verilog and auCdl netlisters. Similar to verilog netlister now it is a requirement for VHDL netlister to have a compiled view i.e. netlist.oa file in the entity view directory or any other stopping view directory. A textual view no more works for netlisting purpose using VHDL toolbox.
A quick way of compiling the stopping view of a given library is using below SKILL code:
- ---------------------------x Copy From Here x------------------
/*************************************************************************
- DISCLAIMER: The following code is provided for Cadence customers *
- to use at their own risk. The code may require modification to *
- satisfy the requirements of any user. The code and any modifications *
- to the code may not be compatible with current or future versions of *
- Cadence products. THE CODE IS PROVIDED "AS IS" AND WITH NO WARRANTIES, *
- INCLUDING WITHOUT LIMITATION ANY EXPRESS WARRANTIES OR IMPLIED *
- WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE. *
- /
procedure(CCScreateOA(lib viewName)
let(()
foreach(cell ddGetObj(lib)~>cells
if(member(viewName cell~>views~>name) then
vmsUpdateCellViews(?lib lib ?cell cell~>name ?view viewName)
)
)
))
- ---------------------------x Copy Till Here x------------------
Load the SKILL code in CIW and then call:
CCScreateOA("mylib" "arc_stop")
arc_stop view of all the cells of library mylib will be compiled. To compile an individual cell you can use:
vmsUpdateCellViews(?lib "mylib" ?cell "buf" ?view "arc_stop")
Or, open the textual view using Library Manager and then Save and Quit in IC6.1.5, the compilation will automatically happen and netlist.oa will get generated for that view.
Since VHDL is not a case sensitive language if you have mixed case for pin names in your entity or architecture view then please specify the below variable in CIW before doing the compilation of views:
vhdlKeepCaseAsNC=t
Otherwise, you may encounter below messages:
WARNING (OSSHNL-259): Failed to generate netlist as terminal 'Y' of instance 'f5' in library 'VHDL_In', cell 'fulladder', view 'schematic' has no corresponding terminal in its switch master lib 'VHDL_In', cell 'and2', view 'arc'. This is because there may be issue in placemaster or switch master of this instance or there are unsaved changes. For modified cellview, save the changes.(for schematic view, click 'Check and Save'; for other views, click 'Save'). Otherwise,revisit the design and netlist again.
The reason R&D decided to move to OSS based VHDL netlister is, it is supposedly more robust. Some of the key points are:
• Leverage the common traversal engine – OSS
– Robust and ample support
– Well defined use model
– Accepted by various customers
• Automatic Data Type Propagation
– Data Type propagates from bottom-to-top from ports to connecting nets and onto ports further.
– Allows leaf level to have "any" data type
– Allows leaf level to be of "any" language
• Enhanced error messages
• Advanced signal datatype conflict resolution
• Supports shorting of two port devices