LVS with Black Box

LVS with Black Box

Sometimes, standard cell libraries are given with partial views which do not include schematics and full layouts. In this case, source netlists (from schematic or verilog file) and layout netlists do not have any information inside the cells, thus only the connections at the cell-level can be compared, and the LVS tool (calibre) needs to be told to do so. The steps to make LVS clean with partial views are as follow.

1. Preparation of source netlist

After the place-and-route by Encounter, verilog netlist is generated. To convert the verilog file to netlist(*.cdl, here) for LVS, "v2lvs" command is used. In its simplest form, it is written as,

"v2lvs -v design.v -o design.cdl -s0 VSS -s1 VDD"

Since the cells in the design.cdl file have not been defined yet, a dummy file, "cells.cdl" is necessary.

The followings are enough in "cells.cdl",

.SUBCKT cell_name1 pin1 pin2 pin3 ..

.ENDS

.SUBCKT cell_name2 pin1 pin2 pin3 ..

.ENDS

......

Then, include the following line at the beginning of "design.cdl".

.INCLUDE "cells.cdl"

2. Preparation of layout

Only metal and pin layers are given in the form of *.lef file. Import the lef to layout in the icfb through File-> Import-> LEF, and make sure the metal and pin layers of each cell are mapped to appropriate layers in the layout.

3. Calibre LVS

Open the Calibre LVS.

In "Inputs",

Deselect "Export from schematic viewer", and browse the "design.cdl" above. Select Hierarchical

In "LVS Options -> Include -> Include SVRF Commands", add the following for all cells used

LVS BOX cell_name1

LVS BOX cell_name2 ...

or create a file including all commands, and put the file name in the "Include Rule Files" window.