Synthesized Circuits

Model Sim

First create your verilog module using modelsim.

To do this you first need to load the module for modelsim (Note: A full list of all modules can be found by typing module -v avail and the current loaded modules can be found by typing module -v list). To load this module type:

module load modelsim

This will load the current version of modelsim settings. To run modelsim type:

vsim &

Remember that you should create both the module and a testbench for the module in modelsim. Run the testbench (make sure you have $stop at the end of the testbench) and make sure that the output is as expected.

Design Compiler (Synopsys)

You must first load the module for design compiler by typing the following command:

module load synopsys-synth/2012.06/64b

Next, you will use a premade perl script to run Design Compiler on your verilog module. To do this, you will need the following directories and files setup as shown below. These can be downloaded from this link.

• apr
  • osama.map
  • your_design.conf (you will have to rename this)
  • your_design.io (you will have to rename this)
  • your_design.tcl * (you will have to rename this)
  • v2lvs_osama
• sim
• synth
  • pl_run_synth.pl
  • timing.tcl
  • namingrules.tcl
  • common.tcl
  • default.svf
  • your_module.tcl * (you will have to rename this)
• verilog
  • your_module.v (this is your module file)

To run the design compiler, cd to the synth directory and type:

perl pl_run_synth.pl your_module

Notes:

• Do not at .v to the end of your_module
• The files with an '*' need to be modified to match your cell name (i.e. your_module.v must be inserted where appropriate into these files)

Encounter (APR - Auto Place & Route)

First, you must load the module:

module load edi

To launch Encounter type:

encounter

Do not use the ampersand (&) to run encounter in the background or else it will just freeze on you.

Once in encounter, you type:

source file_name.tcl

9M_6X1Z1U wb/9m/9M_6X1Z1U is the design file from ARM (2013)